1. Field of the Invention
The invention relates to a receiving circuit, and more particularly to a receiving circuit compatible with core circuits with different specification requirements.
2. Description of the Related Art
FIG. 1 shows a conventional receiving circuit having multiple output signals. Referring to FIG. 1, a receiving circuit 1 receives an input signal SIN and a reference signal SREF and includes path units 10 and 11 which generate output signals OUT10 and OUT11 respectively. The receiving circuit 1 is a part of an input/output (I/O) circuit which a core circuit is coupled to. The core circuit coupled to the receiving circuit 1 receives the output signal OUT10 and/or OUT11. The path unit 10 is used to generate the output signal OUT10 complying with a stub series terminated logic (SSTL) standard to a core circuit, such as a double data rate I (DDRI), DDRII, or DDRIII memories. The path unit 10 receives both of the input signal SIN and the reference signal SREF according to the SSTL standard and includes a differential receiver 100 and a level shifter 101. The path unit 11 is used to generate the output signal OUT11 complying with a low voltage transistor to transistor logic (LVTTL) standard to a core circuit, such as a mobile DDR or single data rate (SDR) memory. The path unit 11 receives only the input signal SIN according to the LVTTL standard and includes a single-end receiver 110 and a level shifter 111. Both of the differential receiver 100 and the single-end receiver 110 operate at an I/O power domain and receive an I/O power voltage VDDH and an I/O ground voltage VSSH of the I/O power domain. The value of the I/O power voltage VDDH can be determined according to the specification of a core circuit coupled to the receiving circuit 1. For example, the I/O power voltage VDDH can be 3.3V for an SDR memory, 2.5V for a DDRI memory, 1.8V for a DDRII or mobile DDR memory, or 1.5V for a DDRIII memory. The level shifters 101 and 111 receive the I/O power voltage VDDH and the I/O ground voltage VSSH of the I/O power domain and further receive a core power voltage VDDL and a core ground voltage VSSL of a core power domain. The level shifters 101 and 111 shift levels of respective output signals of the receivers 100 and 110, so that the output signals OUT10 and OUT11 respectively generated by the level shifters 101 and 111 are in the core power domain. The core circuit receives the output signal OUT10 or OUT11 according to its specification requirements.
Referring to FIG. 1 and FIGS. 2A˜2I, the differential receiver 100 includes positive input terminal (+) (represented by DP in FIGS. 2A˜2I) and negative input terminal (−) (represented by DN in FIGS. 2A˜2I) for respectively receiving the input signal SIN and the reference signal SREF and further includes an output terminal (represented by OUT in FIGS. 2A˜2I). FIGS. 2A˜2I show different circuitries of the differential receiver 100. The differential receiver 100 operates at the I/O power domain. The circuitries in FIGS. 2A˜2I are formed by thick gate I/O devices (i.e. devices with thick gate dielectric) to tolerate the I/O power voltage VDDH and an I/O ground voltage VSSL of the I/O power domain and the incoming signals SIN and SREF. Thus, the differential receiver 100 occupies a large area.
Memories with low power and high speed data-rates, such as low power double data rate II (LPDDRII) memory, becomes more and more popular. An LPDDRII memory adopts signals complying with the SSTL standard, thus the path unit 10 may be used for the LPDDRII memory. According to the specification of an LPDDRII memory, the value of the I/O power voltage VDDH must be lowered to 1.2V. Thus, when the receiving circuit 1 is requested to be compatible with an LPDDRII memory and other memories of different specifications, such as a mobile DDR, a DDRII, and DDRIII memories, meeting the high speed data-rate requirements of the LPDDRII memory becomes difficult. Specifically, in the differential receiver 100 of the path unit 10 formed by the thick gate I/O devices, at least three thick gate I/O devices are cascaded, resulting in insufficient voltage headroom.
Thus, it is desired to provide a receiving circuit compatible with core circuits having different specification requirements, wherein the core circuits in particular, include a low voltage core circuit.